1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly to a plasma display panel that is adaptive for improving yield and mass productivity and a fabricating method thereof.
2. Description of the Related Art
A plasma display panel (hereinafter ‘PDP’) has light emission of phosphorus caused by ultraviolet rays of 147 nm that is generated upon discharge of inert mixed gas such as He+Xe, Ne+Xe, He+Xe+Ne, thereby displaying a picture including characters or graphics. Such a PDP is easy to be made into a thin-film and large-dimension type of it. Moreover, the PDP provides a very improved picture quality owing to recent technical development.
Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a sustain electrode pair 4 formed on an upper substrate 16 and an address electrode 2 formed on a lower substrate 14.
Each of the sustain electrode pair 4 includes a transparent electrode 4A of indium tin oxide ITO and a metal bus electrode 4B formed at one side of the edge of the transparent electrode 4A. An upper dielectric layer 12 and a protective film 10 are deposited on the upper substrate 16 where the sustain electrode pair 4 has been formed. Wall charges generated upon plasma discharge are accumulated in the upper dielectric layer 12. The protective film 10 prevents the upper dielectric layer 12 and the sustain electrode pair 4 from being damaged due to sputtering generated upon plasma discharge, and in addition, it increases the emission efficiency of secondary electron. The protective film 10 is normally magnesium oxide MgO.
A lower dielectric layer and barrier ribs 8 are formed on the lower substrate 14 where address electrode 2 has been formed, and a phosphorus 6 is formed on the surface of the lower dielectric layer 18 and the barrier ribs 8. The address electrode 2 is orthogonal to the sustain electrode pair 4. The barrier ribs 8 are formed along the address electrode 2 to prevent the ultraviolet ray and visible ray generated by discharge from leaking out to adjacent discharge cells. The phosphorus 6 is excited by the vacuum ultraviolet ray generated upon plasma discharge to generate any one of red, green or blue visible ray.
Inert mixed gas such as He+Xe, Ne+Xe, He+Xe+Ne is injected for discharge into a discharge space of the discharge cell provided between the upper/lower substrate 16, 14 and the barrier ribs 8.
On the other hand, the lower substrate 14 where the address electrode 2 has been formed is joined with the upper substrate 16 where the sustain electrode pair 4Y, 4Z has been formed, as shown in FIG. 2, by a sealing layer 50.
FIGS. 3A to 3D are sectional diagrams representing a sealing process of PDP of prior art.
Firstly, the sustain electrode pair 4Y, 4Z and the upper dielectric layer 12 are formed on the upper substrate 16, as shown in FIG. 3A.
The sealing layer 50, as shown in FIG. 3B, is formed on the upper substrate 16 where the upper dielectric layer 12 has been formed. The sealing layer 50 is formed by spreading sealing-paste in use of a screen printing or a dispenser, wherein the sealing-paste is formed by mixing glass powder, solvent and binder together.
Subsequently, under the environment of 200˜300° C., the protective film 10 is formed on the upper substrate 16 in use of E-beam deposition or sputtering methods, as shown in FIG. 3C.
Subsequently, the upper substrate 16 is aligned with the lower substrate 14 while the upper substrate 16 where the sealing layer 50 has been formed is pressed against and joined with the lower substrate 14. The aligned upper substrate 16 and lower substrate 14 are fired to remove a large amount of solvent and organic material which are contained within the sealing layer 50, thereby joining the upper/lower substrate 16, 14, as shown in FIG. 3D.
However, after the protective film 10 is formed under the environment of 200–300° C., there occurs a crack in the area of the upper substrate 16 contacted with the sealing layer 50 due to the difference of thermal expansion coefficient between the upper substrate 16 and the sealing layer 50 in the course that it cools down to normal temperature. The difference of such thermal expansion coefficients generates partial thermal stress on a part where the upper substrate 16 is in contact with the sealing layer 50. There is generated a thermal stress which is relatively bigger in the upper substrate 16 than in the sealing layer 50, wherein the upper substrate 16 has relatively bigger thermal expansion coefficient than the sealing layer 50, and the thermal stress causes the crack to be generated in the upper substrate 16.
Accordingly, there is a problem that the yield and mass productivity of PDP is decreased.